1. Field of the Invention
The present invention relates generally to a semiconductor device including a MOS (Metal Oxide Semiconductor) transistor and a method of manufacturing such a semiconductor device and, more particularly to technology for achieving higher performance and higher reliability of the MOS transistor by including a neutral impurity layer within a semiconductor substrate.
2. Description of the Background Art
As a highly reliable MOS field effect transistor, such an LDD (Lightly Doped Drain) structure as shown in FIG. 1 and described in, for example, "IEEE Transactions on Electron Devices", ED-27 (1980), p. 1359 has conventionally been employed in general. Referring to FIG. 1, in this MOS field effect transistor, a gate electrode 4 is patterned on a surface of a p well region 2 in a semiconductor substrate 1, with a gate insulator film 3 interposed therebetween. Sidewall spacers 5 and 5 are formed on opposite sidewalls of gate electrode 4. n type impurity layers 6 and 6 of low concentration are formed in the surface of p well region 2 beneath sidewall spacers 5 and 5. n type impurity layers 7 and 7 of high concentration are formed in external regions of n type impurity layers 6 and 6 relative to a portion below gate electrode 4. The structure shown in FIG. 1 has a specific disadvantage of the LDD structure that a mode in which current drivability is degraded, i.e., an increase in parasitic resistance takes place. The increase in parasitic resistance is due to high resistance of n type impurity layers 6 and 6 of low concentration and an effect that electrons are captured in sidewall spacers 5 and 5 located on n type impurity layers 6 and 6. The latter mechanism in particular is that if electrons are captured in both sidewall spacers 5 and 5 on n type impurity layers 6 and 6, electrons in n type impurity layers 6 and 6 adjacent to sidewall spacers 5 and 5 are expelled by repulsive force, whereby a resistance value of n type impurity layers 6 and 6 effectively increases, causing a degradation in current level.
An improvement of such structure is an MLDD (Moderately Lightly Doped Drain) structure shown in, for example, "VLSI SYMPOSIUM (1985)", p. 116. This structure aims to inhibit the above-described degradation mode by setting the concentration of n type impurity layers 6 and 6 to be slightly higher than the concentration of n type impurities, at which a substrate current adopted in the conventional LDD structure becomes minimum, thereby shifting a maximal electric field position further closer to gate electrode 4 and reducing electrons to be injected and captured in sidewall spacers 5 and 5.
As a MOS field effect transistor for inhibiting the degradation mode more effectively, the one employing a gate overlap type LDD structure is described in, for example, "VLSI SYMPOSIUM (1989)", p. 33. In this structure, referring to FIG. 2, with n type impurity layers 6 and 6 of low concentration overlapped with gate electrode 4, the position of a maximum electric field at which hot carriers are generated is shifted directly below gate electrode 4, thereby decreasing the maximum electric field and also preventing electrons from being captured in sidewall spacers 5 and 5.
In the MOS field effect transistor, if neutral impurities such as silicon (Si) or germanium (Ge) are implanted before formation of an impurity layer in source/drain regions, to form a neutral impurity layer 8 as shown in FIG. 3, longitudinal or lateral diffusion of n type impurities in the source/drain regions is inhibited, thereby inhibiting a degradation in characteristics due to a short channel effect. This is described in, for example, "IEEE Electron Device Letters", VOL. 9, No. 7, 1988, p. 343. This document presents a graph shown in FIGS. 4A and 4B as data indicating an effect of Ge doping. FIG. 4A shows impurity profile in a direction of the depth of the semiconductor substrate subjected to annealing at 900.degree. C. in 12 minutes, with respect to the case of only phosphorus doping (implantation energy of 45 KeV, dose of 2.5.times.10.sup.15 /cm.sup.2) and the case with Ge doping (implantation energy of 125 KeV, dose of 5.0.times.10.sup.15 /cm.sup.2) added to the same phosphorus doping. FIG. 4B shows dependence of a threshold voltage shift (.DELTA.V.sub.th) on effective channel length with respect to the above -respective cases.
In addition, the fact that a transistor having a channel region or part of the region implanted with neutral impurities such as Ge is particularly effective for inhibition of hot carriers is described in, for example "IEEE Electron Device Letters", VOL. 11, No. 1, 1990, p. 45.
A conventional LDD structure has an advantage that since n type impurity layers 6 and 6 of low concentration are formed of phosphorus being impurities of a large diffusion coefficient, a moderate concentration gradient and a greater effect of reducing an electric field are achieved, whereas it has a disadvantage that a short channel effect is more prominent in a small transistor. That is, such a phenomenon occurs that the threshold voltage (V.sub.th) of the transistor rapidly falls as the channel length (L) of the transistor becomes smaller. When the channel length (L) used in practice is in a region where the falling of threshold voltage V.sub.th takes place, as threshold voltage V.sub.th falls more rapidly, the manufacture of the channel length becomes less uniform, thereby causing a greater variation in transistor characteristics and a greater decrease in yield of performance. Thus, if the amount of implantation of phosphorus is reduced in order to suppress the short channel effect, this results in an increase in resistance (parasitic resistance) of n type impurity layers 6 and 6 of low concentration and thus a degradation in current drivability.
In the above-described gate overlap type LDD structure also, the concentration of the n type impurity layers of low concentration formed of phosphorus is not allowed to be considerably high in order to suppress the short channel effect. Thus, such an attempt is considered that n type impurity layers of low concentration is formed of arsenic having a smaller diffusion coefficient, thereby allowing a greater improvement in the falling of threshold voltage V.sub.th and a greater decrease in parasitic capacitance as compared to the case with phosphorus. However, arsenic with a small diffusion coefficient cannot achieve a sufficient concentration gradient or a sufficient effect of reducing an electric field, resulting in a difficulty of sufficiently reducing a substrate current due to hot carriers.
Further, in any conventional LDD structures, the rate of hot carrier generation is suppressed by the reduced electric field effect; however, phonon scattering, i.e., scattering of electrons in crystal caused by lattice vibration decreases at lower temperatures, and the hot carrier generation rate increases again. Thus, there is a disadvantage that hot carrier characteristics are still deteriorated.
Although the transistor having the channel region or part of the region implanted with neutral impurities such as Ge is effective for the inhibition of hot carriers, such an effect is approximately half or one third of the effect of the LDD structure, and there is a limitation in reducing the hot carrier effect of a transistor of a submicron level only by neutral impurities such as Ge.
The amount of Ge implantation for suppressing such a short channel effect requires approximately 10.sup.19 -10.sup.20 /cm.sup.3, however, the implantation of such high concentration neutral impurities into the channel region causes defects or stresses in the channel region, thereby greatly affecting transistor characteristics. More specifically, since there is a difference between an optimal implantation amount for suppressing the longitudinal or lateral diffusion of n type impurities in the source/drain regions to suppress the short channel effect and an optimal implantation amount into the channel region for suppressing hot carriers, both optimum conditions cannot be satisfied by a single implantation.